Voltage quadrupler pdf
Voltage multiplier has different stages. Each stage is made up of one diode and one capacitor. These arrangements of diodes and capacitors make it possible to produce rectified and filtered output voltage whose amplitude peak value is larger than the input AC voltage.
Voltage multipliers are classified into four types:. As its name suggests, a half-wave voltage doubler is a voltage multiplier circuit whose output voltage amplitude is twice that of the input voltage amplitude. A half-wave voltage doubler drives the voltage to the output during either positive or negative half cycle. The half-wave voltage doubler circuit consists of two diodes, two capacitors, and AC input voltage source.
During positive half cycle:. The circuit diagram of the half-wave voltage doubler is shown in the below figure. During the positive half cycle, diode D 1 is forward biased. So it allows electric current through it. This current will flows to the capacitor C 1 and charges it to the peak value of input voltage I.
However, current does not flow to the capacitor C 2 because the diode D 2 is reverse biased. So the diode D 2 blocks the electric current flowing towards the capacitor C 2. Therefore, during the positive half cycle, capacitor C 1 is charged whereas capacitor C 2 is uncharged.
During negative half cycle:. During the negative half cycle, diode D 1 is reverse biased. So the diode D 1 will not allow electric current through it. Therefore, during the negative half cycle, the capacitor C 1 will not be charged. However, the charge V m stored in the capacitor C 1 is discharged released. On the other hand, the diode D 2 is forward biased during the negative half cycle.
So the diode D 2 allows electric current through it. This current will flows to the capacitor C 2 and charges it. The capacitor C 2 charges to a value 2V m because the input voltage V m and capacitor C 1 voltage V m is added to the capacitor C 2. Hence, during the negative half cycle, the capacitor C 2 is charged by both input supply voltage V m and capacitor C 1 voltage V m.
Therefore, the capacitor C 2 is charged to 2V m. If a load is connected to the circuit at the output side, the charge 2V m stored in the capacitor C 2 is discharged and flows to the output. During the next positive half cycle, diode D 1 is forward biased and diode D 2 is reverse biased. So the capacitor C 1 charges to V m whereas capacitor C 2 will not be charged. However, the charge 2V m stored in the capacitor C 2 will be discharged and flows to the output load.
Thus, the half-wave voltage doubler drives a voltage of 2V m to the output load. The capacitor C 2 gets charged again in the next half cycle. The voltage 2V m obtained at the output side is twice that of the input voltage V m.
The capacitors C 1 and C 2 in half wave-voltage doubler charges in alternate half cycles. The output waveform of the half-wave voltage doubler is almost similar to the half wave rectifier with filter.
The only difference is the output voltage amplitude of the half-wave voltage doubler is twice that of the input voltage amplitude but in half wave rectifier with filter, the output voltage amplitude is same as the input voltage amplitude. The half-wave voltage doubler supplies the voltage to the output load in one cycle either positive or negative half cycle. In our case, the half-wave voltage doubler supplies the voltage to the output load during positive half cycles.
Therefore, the output signal regulation of the half-wave voltage doubler is poor. Advantages of half-wave voltage doubler. High voltages are produced from the low input voltage source without using the expensive high voltage transformers. Disadvantages of half-wave voltage doubler. Large ripples unwanted fluctuations are present in the output signal.
The full-wave voltage doubler consists of two diodes, two capacitors, and input AC voltage source. During the positive half cycle of the input AC signal, diode D 1 is forward biased. So the diode D 1 allows electric current through it. On the other hand, diode D 2 is reverse biased during the positive half cycle. So the diode D 2 does not allow electric current through it.
Therefore, the capacitor C 2 is uncharged. During the negative half cycle of the input AC signal, the diode D 2 is forward biased. This current will flows to the capacitor C 2 and charges it to the peak value of the input voltage I. On the other hand, diode D 1 is reverse biased during the negative half cycle.
So the diode D 1 does not allow electric current through it. Thus, the capacitor C 1 and capacitor C 2 are charged during alternate half cycles. The output voltage is taken across the two series connected capacitors C 1 and C 2. If no load is connected, the output voltage is equal to the sum of capacitor C 1 voltage and capacitor C 2 voltage I.
When a load is connected to the output terminals, the output voltage V o will be somewhat less than 2V m. The circuit is called full-wave voltage doubler because one of the output capacitors is being charged during each half cycle of the input voltage.
The voltage tripler can be obtained by adding one more diode-capacitor stage to the half-wave voltage doubler circuit.
During first positive half cycle:. The right end is grounded by the conducting D2. The left end is charged at the negative peak of the AC input. This is the operation of the clamper. During the positive half cycle, the half-wave rectifier comes into play at Figure above c.
Diode D2 is out of the circuit since it is reverse biased. C2 is now in series with the voltage source. Note the polarities of the generator and C2, series aiding. Thus, rectifier D1 sees a total of 10 V at the peak of the sinewave, 5 V from generator and 5 V from C2. Waveform v 2 is the output of the doubler, which stabilizes at 10 V 8. Voltage doubler: v 4 input. The full-wave voltage doubler is composed of a pair of series stacked half-wave rectifiers. Figure below The corresponding netlist is in Figure below.
The bottom rectifier charges C1 on the negative half cycle of input. The top rectifier charges C2 on the positive halfcycle. Each capacitor takes on a charge of 5 V 4. The output at node 5 is the series total of C1 C2 or 10 V 8. Full-wave voltage doubler consists of two half-wave rectifiers operating on alternating polarities. Note that the output v 5 Figure below reaches full value within one cycle of the input v 2 excursion. Full-wave voltage doubler: v 2 input, v 3 voltage at mid point, v 5 voltage at output.
Figure below illustrates the derivation of the full-wave doubler from a pair of opposite polarity half-wave rectifiers a. The negative rectifier of the pair is redrawn for clarity b. Both are combined at c sharing the same ground. At d the negative rectifier is re-wired to share one voltage source with the positive rectifier. The ground reference point is moved so that 10 V is available with respect to ground.
Full-wave doubler: a Pair of doublers, b redrawn, c sharing the ground, d share the same voltage source. A voltage tripler Figure below is built from a combination of a doubler and a half wave rectifier C3, D3. The half-wave rectifier produces 5 V 4. The doubler provides another 10 V 8. The netlist is in Figure below. Voltage tripler composed of doubler stacked atop a single stage rectifier.
Note that V 3 in Figure below rises to 5 V 4. Input v 4 is shifted upward by 5 V 4. And 5 V more at v 1 due to the clamper C2, D2. D1 charges C1 waveform v 2 to the peak value of v 1. Voltage tripler: v 3 half-wave rectifier, v 4 input 5 V, v 1 clamper, v 2 final output. A voltage quadrupler is a stacked combination of two doublers shown in Figure below.
Each doubler provides 10 V 8. Voltage quadrupler, composed of two doublers stacked in series, with output at node 2. The waveforms of the quadrupler are shown in Figure below. Two DC outputs are available: v 3 , the doubler output, and v 2 the quadrupler output. Strictly v 4 is not a clamper output. It is simply the AC voltage source in series with the v 3 the doubler output. Voltage quadrupler: DC voltage available at v 3 and v 2. Intermediate waveforms: Clampers: v 5 , v 4 , v 1.
Some notes on voltage multipliers are in order at this point.
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